21405 三次元実装用Cu貫通電極形成のための電解めっき技術(デバイス&配線技術1,OS.1 機械工学が支援する微細加工技術(半導体・MEMS・NEMS),学術講演)

概要

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Three-dimensional (3D) packaging structure will lead to minimal inter-chip connection space and length, and reduce interconnection delay. Through silicon vias(TSV) have good potential for implementation of 3D packaging. Electroplating technology for TSV-filling with copper(Cu) is one of strong candidates. We evaluated and optimized the influence of paddle agitation and plating current to give good via-filling with the dip type plating machine. As a result, a complete TSV-filling was achieved by bottom-up plating in very short time. In addition, an electro potential regulation plate was installed in the cell for improving plated film thickness uniformity on the wafer. Vias on silicon wafer were successfully filled with copper in wafer level test. In this paper, reliable high-speed via-filling results and their conditions were shown and discussed.
一般社団法人日本機械学会の論文
2008-03-13