RC-008 Rapid Design of a Multiprocessor System for a JPEG Decoder on FPGA
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概要
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Multiple cores system at a lower frequency is efficient approach to increase performance where power consumption is limiting performance. Meanwhile FPGA is capable of providing designers with several benefits in system design, which decreasing the design cost and time for market. This paper demonstrates the design of an FPGA-based embedded multiprocessor system integrating up to three processor cores into a system for a JPEG Decoder. According to the process of JPEG decoding, task sharing is proposed to make the multi-core work in parallel without conflicts. The application program to decode a DCT-based JPEG compressed image is successfully implemented on the FPGA board with the 40MHz operating frequency. Based on the proposed hardware and software, the performance increasing of decoding is approximately close to 2.6 times in a large resolution image and up to 10% power saving without performance loss compared to the uni-core system.
- 2008-08-20
著者
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Watanabe Takahiro
Graduate School Of Information Production And Systems Waseda Univ.
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Watanabe Takahiro
Graduation School Of Ips Waseda University
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Cao Dawei
Graduation School of IPS, Waseda University
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Chen Keyan
Graduation School of IPS, Waseda University
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Cao Dawei
Graduation School Of Ips Waseda University
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Watanabe Takahiro
Graduate School Of Information Production And System Waseda University
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Chen Keyan
Graduation School Of Ips Waseda University
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