A Cost Effective Interconnection Network for Reconfigurable Computing Processor in Digital Signal Processing Applications(<Special Section>Novel Device Architectures and System Integration Technologies)
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概要
- 論文の詳細を見る
In this paper, a novel cost effective interconnection network for two-way pipelined SIMD-based reconfigurable computing processor is proposed. Our reconfigurable computing engine is composed of the SIMD-based function units, flexible interconnection networks, and two-bank on-chip memories. In order to connect the function units, the reconfigurable network is proposed to connect all neighbors of each function unit. The proposed interconnection network is a kind of full and bidirectional connection with the data duplication to perform the data-parallelism applications efficiently. Moreover, it is a multistage network to accomplish the high flexibility and low hardware cost.
- 社団法人電子情報通信学会の論文
- 2006-11-01
著者
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Chen Lien-fei
Department Of The Electrical Engineering National Chung Hsing University
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LAI Yeong-Kang
Department of the Electrical Engineering, National Chung Hsing University
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CHEN Jian-Chou
Department of the Electrical Engineering, National Chung Hsing University
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CHIU Chun-Wei
Department of the Electrical Engineering, National Chung Hsing University
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Chen Lien-fei
Department Of Electrical Engineering National Chung Hsing University
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Chen Jian-chou
Department Of The Electrical Engineering National Chung Hsing University:(present Office)etron Techn
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Chiu Chun-wei
Department Of The Electrical Engineering National Chung Hsing University:(present Office)winbond Ele
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Lai Yeong-kang
Department Of The Electrical Engineering National Chung Hsing University
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Lai Yeong-kang
Department Of Electrical Engineering National Chung Hsing University
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Chen Jian-chou
Department Of Electrical Engineering National Chung Hsing University
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