Hardware Implementation of an Inverse Function Delayed Neural Network Using Stochastic Logic(Biocybernetics, Neurocomputing)
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概要
- 論文の詳細を見る
In this paper, the authors present a new digital circuit of neuron hardware using a field programmable gate array (FPGA). A new Inverse function Delayed (ID) neuron model is implemented. The Inverse function Delayed model, which includes the BVP model, has superior associative properties thanks to negative resistance. An associative memory based on the ID model with self-connections has possibilities of improving its basin sizes and memory capacity. In order to decrease circuit area, we employ stochastic logic. The proposed neuron circuit completes the stimulus response output, and its retrieval property with negative resistance is superior to a conventional nonlinear model in basin size of an associative memory.
- 社団法人電子情報通信学会の論文
- 2006-09-01
著者
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Hayakawa Yoshihiro
Laboratory For Brainware Systems Laboratory For Nanoelectronics And Spintronics Research Institute O
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Hayakawa Yoshihiro
Tohoku Univ. Sendai‐shi Jpn
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SATO Shigeo
Research Institute of Electrical Communication, Tohoku University
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NAKAJIMA Koji
Research Institute of Electrical Communication, Tohoku University
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LI Hongge
School of Engineering, Tohoku University
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HAYAKAWA Yoshihiro
Research Institute of Electrical Communication, Tohoku University
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Hayakawa Yoshihiro
Research Institute Of Electrical Communication Tohoku University
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Li Hongge
School Of Engineering Tohoku University
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Nakajima Koji
Tohoku Univ. Sendai‐shi Jpn
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Nakajima Koji
Research Institute Of Electrical Communication Tohoku University
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Sato Shigeo
Research Institute Of Electrical Communication Tohoku University
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Sato Shigeo
Research And Development Center Tdk Corp.
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