Adaptive Low-Error Fixed-Width Booth Multipliers(Circuit Theory)

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概要

• 論文の詳細を見る

• In this paper, we propose two 2's-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best error-compensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65-84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates.

• 社団法人電子情報通信学会の論文
• 2007-06-01

著者

• KUO Sy-Yen

  Department of Electrical Engineering and Graduate Institute of Electronic Engineering, National Taiw

• Song Min-an

  Department Of Electrical Engineering National Taiwan University

• Kuo Sy-yen

  Department Of Electrical Engineering And Graduate Institute Of Electronic Engineering National Taiwa

• VAN Lan-Da

  Department of Computer Science and Information Engineering, National Taiwan University of Science an

• Van Lan‐da

  Department Of Computer Science And Information Engineering National Taiwan University Of Science And

• Kuo Sy-yen

  Department Of Computer Science National Chiao Tung University

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