VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design(Digital Signal Processing)

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概要

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• In this paper, we propose one low-computation cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFT/IDFT architectures, the proposed recursive architecture achieves a reduction in computation-cycle by half. Appling this novel low-computation cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77μW under 1.2V@20MHz in TSMC 0.13 1P8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-computation cycle architecture.

• 社団法人電子情報通信学会の論文
• 2007-08-01

著者

• VAN Lan-Da

  Department of Computer Science and Information Engineering, National Taiwan University of Science an

• Yu Yuan-chu

  Department Of Electrical And Control Engineering National Chiao-tung University

• Van Lan-da

  Department Of Computer Science National Chiao-tung University

• LIN Chin-Teng

  Dean Office of Academic Affairs, National Chiao-Tung University

• Lin Chin-teng

  Dean Office Of Academic Affairs National Chiao-tung University

関連論文

• Adaptive Low-Error Fixed-Width Booth Multipliers(Circuit Theory)
• VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design(Digital Signal Processing)

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