Achieving Fault Tolerance in Pipelined Multiprocessor Systems

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概要

• 論文の詳細を見る

• This paper focuses on recovering from processor transient faults in pipelined multiprocessor systems. A pipelined machine may employ out of order execution and branch prediction techniques to increase performance, thus a precise computation state would not be available. We propose an efficient scheme to maintain the precise computation state in a pipelined machine. The goal of this paper is to implement checkpointing and roll-back recovery utilizing the technique of precise interrupt in a pipelined system. Detailed analysis is included to demonstrate the effectiveness of this method.

• 社団法人電子情報通信学会の論文
• 1997-06-25

著者

• KUO Sy-Yen

  Department of Electrical Engineering and Graduate Institute of Electronic Engineering, National Taiw

• LIN Jeng-Ping

  Department of Electrical Engineering, National Taiwan University

• Kuo S‐y

  National Taiwan Univ. Taipei Twn

• Kuo Sy-yen

  Department Of Electrical Engineering And Graduate Institute Of Electronic Engineering National Taiwa

• Lin Jeng-ping

  Department Of Electrical Engineering National Taiwan University

• Kuo Sy-yen

  Department Of Computer Science National Chiao Tung University

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• Achieving Fault Tolerance in Pipelined Multiprocessor Systems
• Adaptive Low-Error Fixed-Width Booth Multipliers(Circuit Theory)
• 信頼性教室 Software Reliability:Theory and Modeling

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