Zero-Skew Driven Buffered RLC Clock Tree Construction(VLSI Design Technology and CAD)

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概要

• 論文の詳細を見る

• In nature an unbalanced clock tree exists in a SoC because the clock sinks of IPs have distinct input capacitive loads and internal delays. The construction of a bottom-up RLC clock tree with minimal clock delay and zero skew is crucial to ensure good SoC performance. This study proves that an RLC clock tree construction always has no zero skew owing to skew upward propagation. Specifically, this study proposes the insertion of two unit-size buffers associated with the binary search for a tapping point into each pair of subtrees to interrupt the non-zero skew upward propagation. This technique enables reliable construction of a buffered RLC clock tree with zero skew. The effectiveness of the proposed approach is demonstrated by assessing benchmarks.

• 社団法人電子情報通信学会の論文
• 2007-03-01

著者

• Lee Trong-yen

  Graduate Institute Of Computer And Communication National Taipei University Of Technology

• Tsai Chia-chun

  Dept. Of Computer Science And Information Eng. Nanhua University

• WU Jan-Ou

  Department of Electronic Engineering, De Lin Institute of Technology

• WU Jan-Ou

  Graduate Institute of Computer and Communication, National Taipei University of Technology

• KUO Chung-Chieh

  Graduate Institute of Computer and Communication, National Taipei University of Technology

• Wu Jan-ou

  Department Of Electronic Engineering De Lin Institute Of Technology

• Kuo Chung-chieh

  Graduate Institute Of Computer And Communication National Taipei University Of Technology

関連論文

• GDME : Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay
• Zero-Skew Driven Buffered RLC Clock Tree Construction(VLSI Design Technology and CAD)
• Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement

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