Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement

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概要

• 論文の詳細を見る

• As the VLSI manufacturing technology shrinks to 65nm and below, reducing the yield loss induced by via failures is a critical issue in design for manufacturability (DFM). Semiconductor foundries highly recommend using the double-via insertion (DVI) method to improve yield and reliability of designs. This work applies the DVI method in the post-stage of an X-architecture clock routing for double-via insertion rate improvement. The proposed DVI-X algorithm constructs the bipartite graphs of the partitioned clock routing layout with single vias and redundant-via candidates (RVCs). Then, DVI-X applies the augmenting path approach associated with the construction of the maximal cliques to obtain the matching solution from the bipartite graphs. Experimental results on benchmarks show that DVI-X can achieve higher double-via insertion rate by 3% and less running time by 68% than existing works. Moreover, a skew tuning technique is further applied to achieve zero skew because the inserted double vias affect the clock skew.

• （社）電子情報通信学会の論文
• 2011-02-01

著者

• Lee Trong-yen

  Graduate Institute Of Computer And Communication National Taipei University Of Technology

• Tsai Chia-chun

  Dept. Of Computer Science And Information Eng. Nanhua University

• KUO Chung-Chieh

  Graduate Institute of Computer and Communication, National Taipei University of Technology

• Kuo Chung-chieh

  Graduate Institute Of Computer And Communication National Taipei University Of Technology

• Tsai Chia-chun

  Department Of Computer Science And Information Engineering Nanhua University

関連論文

• GDME : Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay
• Zero-Skew Driven Buffered RLC Clock Tree Construction(VLSI Design Technology and CAD)
• Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement

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