True 50% Duty-Cycle SSH and SHH SiGe BiCMOS Divide-by-3 Prescalers(<Special Section>Analog Circuit and Device Technologies)

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概要

• 論文の詳細を見る

• Four 50% duty-cycle divide-by-3 prescalers-positively/negatively triggered sample-sample-hold (SSH) and sample-hold-hold (SHH) prescalers-are designed based on the current switchable D flip-flops and discussed in this paper. The positively triggered SSH and SHH prescalers are fabricated using the 0.35-μm SiGe BiCMOS technology and measured by the real-time oscilloscope and the spectrum analyzer. The SHH prescaler is our proposed structure and demonstrated in this paper. According to the measurement results, under the condition of the same input power, its maximum operation frequency is twice as high as that of the SSH prescaler thanks to better signal synchronization. At 2.7V supply, the SSH prescaler operates from 500MHz to 2GHz as the SHH prescaler performs from 1GHz to 3.4GHz. The input sensitivity level of both structures is about -5dBm, while the maximum output power is also about -5dBm. The core current consumption is 4.538mA and 4.258mA for the SSH and SHH prescalers, respectively.

• 社団法人電子情報通信学会の論文
• 2006-06-01

著者

• MENG Chinchun

  Department of Communication Engineering, National Chiao Tung University

• Meng Chinchun

  Department Of Communication Engineering National Chiao Tung University

• Chen Wei-yu

  Department Of Communication Engineering National Chiao Tung University

• TSENG Sheng-Che

  Department of Communication Engineering, National Chiao Tung University

• Tseng Sheng-che

  Department Of Communication Engineering National Chiao Tung University

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