Multilevel dual-channel NAND flash memories with high read and program verifying speeds utilizing asymmetrically-doped channel regions

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概要

• 論文の詳細を見る

• The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the high-speed multilevel reading with a wider current sensing margin and the high-speed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed.

• 社団法人電子情報通信学会の論文
• 2009-06-17

著者

• You J.

  Division of Electronics and Computer Engineering, Hanyang University

• Lee J.

  Division Of Electronics And Computer Engineering Hanyang University

• KIM T.

  Division of Materials Science and Engineering, Pusan National University

• JANG S.

  Department of Toxicology, National Institute of Safety Research, Seoul

• You J.

  Division Of Electronics And Computer Engineering Hanyang University

• Kwack K.

  Division Of Electronics And Computer Engineering Hanyang University

• Jang S.

  Department Of Nanoscale Semiconductor Engineering Hanyang University

• Kim T.

  Division Of Electronics And Computer Engineering Hanyang University:department Of Nanoscale Semicond

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