Data-Dependent Logic Swing Internal Bus Architecture for Ultralow-Power LSI's(Special Issue on the 1994 VLSI Circuits Symposium)

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概要

• 論文の詳細を見る

• A reduced-swing internal bus scheme is proposed for achieving ultralow-power LSI's. The proposed data-dependent logic swing bus (DDL bus) uses charge sharing between bus wires and an additional bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed bus is reduced to 1/16 that of a conventional bus when used for a 16-b-wide bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-μm CMOS process verify the low-power operation of the proposed bus at an operating frequency of 40MHz with a supply voltage of 3.3V.

• 社団法人電子情報通信学会の論文
• 1995-06-25

著者

• Hatano Yuji

  Central Research Laboratory Hitachi Ltd.

• Misawa Hitoshi

  Hitachi Microcomputer Systems Ltd.

• KOJIMA Hirotsugu

  Semiconductor Research Lab., Re-search and Development Div., Hitachi America, Ltd.

• Hiraki Mitsuru

  Central Research Laboratory, Hitachi, Ltd.

• Akazawa Takashi

  Semiconductor Division, Hitachi, Ltd.

• Kojima H

  Semiconductor Research Laboratory Research And Development Division Hitachi America Ltd.

• Kojima Hirotsugu

  Semiconductor Research Lab. Re-search And Development Div. Hitachi America Ltd.

• Hiraki Mitsuru

  Central Research Laboratory Hitachi Ltd.

• Akazawa Takashi

  Semiconductor Division Hitachi Ltd.

関連論文

• Power Analysis of a Programmable DSP for Architecture and Program Optimization (Special Issue on Low-Power LSI Technologies)
• Data-Dependent Logic Swing Internal Bus Architecture for Ultralow-Power LSI's(Special Issue on the 1994 VLSI Circuits Symposium)
• Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry(Special Issue on the 1994 VLSI Circuits Symposium)

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