Power Analysis of a Programmable DSP for Architecture and Program Optimization (Special Issue on Low-Power LSI Technologies)

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High level power estimation model is indispensable to optimize architecture and programs in terms of power consumption systematically. This paper describes power analysis results of a general purpose programmable DSP using switch level and cell based power simulation. The analysis results help to know characteristics of the DSP components and to establish a power estimation model. A compensation method for the lack of intra-cell capacitance in a cell based simulation is proposed to improve the simulation accuracy within -20% of error against the measured power. We considered that the error is caused by ignoring short circuit Current and is accurate enough for this level of simulation. Through a result of the power breakdown by modules of the DSP obtained by the simulation, it was found that bus power is much less than generally expected (the simulated power is less than 5% of the total), and that the data operation power dominates the chip power (up to 33%) and is strongly data dependent. The reason that the bus power is low is because both of the load capacitance and the activity are low. Some correlation between the number of input signal transitions and the power consumption is found in each of an ALU, register file, and multiplier through further investigation on the data operation modules. The correlation is worthwhile to establish a power estimation model and is eventually useful to optimize a DSP architecture and DSP programs. The importance of power estimation model is demonstrated by showing an example in which we optimize an FIR filter program based upon the analysis results and proposed a direction of architecture optimization.
社団法人電子情報通信学会の論文
1996-12-25

Power Analysis of a Programmable DSP for Architecture and Program Optimization (Special Issue on Low-Power LSI Technologies)

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