An Effective Extraction of Distributed RLC Circuit Model for Multi-level Interconnects by Layout-Fracturing Algorithm

概要

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In this paper, we propose a layout-fracturing algorithm for the estimation of signal delay at multi-level interconnects. The proposed algorithm divides layout into three types of segments, electrical node segments, resistive segments and capacitive segments, for generation of a distributed RLC circuit model. The fractured segments are transferred directly into a complex RLC circuits by PEEC model, and these segments define each simulation domain and the boundary condition for extracting the parasitics in the distributed RLC network. In order to extract a set of resistance, inductance and capacitance, we solve Maxwell's Equation together with continuity equation over dielectrics and conductors medium using the finite element method (FEM). A sampler circuit, which has 24 transistors for a 3.3 V CMOS technology with 0.25 μm feature size, was examined for the application of our approach. In this work, the signal delay of 0.07 ns is induced by the conventional approach. According to our approach, however, signal operation has more signal delay of 0.17 ns. It increased 33% more than the result of the conventional approach.
2002-06-24