Numerical Analysis of Tunneling Current due to Electric Field Concentration at Gate Edge of Polysilicon/SiO_2/Silicon Structures

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概要

• 論文の詳細を見る

• Tunneling current enhancement due to electric field concentration at a gate edge is investigated by numerical calculation. The detailed current distribution and change of current-voltage (I-V) characteristics are calculated for several gate geometries differing in curvature radius. It is Shown that the current density of an MOS structure with an oxide thickness of 12 nm varies by 3 orders of magnitude when the curvature radius at the gate edge changes from 30 nm to 2 nm. A very narrow region of 8 nm at the curvature area is responsible for 80% of the total current between the gate and n^+ region. The calculated change in I-V characteristics is consistent with the experimentally measured I-V curve of a polysilicon gate/SiO_2/n^+-silicon structure.

• 社団法人応用物理学会の論文
• 1994-01-30

著者

• Wake S

  Mitsubishi Electric Corp. Hyogo Jpn

• Wake Setsuo

  Ulsi Development Center Mitsubishi Electric Corp.

• NAKANISHI Kazuya

  NTT System Electronics Laboratories

• Kitabayashi Hiroyuki

  Itami Research Laboratories Sumitomo Electric Industries Ltd.

• Nakanishi K

  Ritsumeikan Univ. Kusatsu Jpn

• Muto Hirotaka

  Central Research Laboratory Mitsubishi Electric Corp.

• KITABAYASHI Hiroyoshi

  Central Research Laboratory, Mitsubishi Electric Corp.

• NAKANISHI Koichiro

  Central Research Laboratory, Mitsubishi Electric Corp.

• WAKE Setsuo

  Kita-Itami Works, Mitsubishi Electric Corp.

• NAKAJIMA Moriyoshi

  Kita-Itami Works, Mitsubishi Electric Corp.

• Kitabayashi H

  Itami Research Laboratories Sumitomo Electric Industries Ltd.

• Nakajima Moriyoshi

  Kita-itami Works Mitsubishi Electric Corp.

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