Efficient Application of Hot-Carrier Reliability Simulation to Delay Library Screening for Reliability of Logic Designs(Electronic Circuits)

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概要

• 論文の詳細を見る

• This paper presents an efficient, application of hot-carrier reliability simulation to delay libraries of 0.18μm and 0.14μm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0 100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.

• 社団法人電子情報通信学会の論文
• 2003-05-01

著者

• Lee Peter

  Semiconductor And Integrated Circuits Hitachi Ltd.:renesas Technology Corporation

• Kondo Yuichi

  Hitachi Ulsi Systems Co.

• YANAGISAWA Kazumasa

  Semiconductor & Integrated Circuits Div., Hitachi Ltd.

• Sato Hisako

  Semiconductor And Integrated Circuits Hitachi Ltd.:graduate School Of Science The University Of Toky

• OHTSUKA Mariko

  Hitachi ULSI Systems Co.

• MAKABE Kazuya

  Semiconductor and Integrated Circuits, Hitachi, Ltd.

• Makabe K

  Semiconductor And Integrated Circuits Hitachi Ltd.:renesas Technology Corporation

• Yanagisawa Kazumasa

  Semiconductor And Integrated Circuits Hitachi Ltd.:renesas Technology Corporation

関連論文

• Low-Power and High-Speed Advantages of DRAM-Logic Integration for Multimedia Systems (Special Issue on Low-Power and High-Speed LSI Technologies)
• Efficient Application of Hot-Carrier Reliability Simulation to Delay Library Screening for Reliability of Logic Designs(Electronic Circuits)
• CMOS Process Compatible ie-Flash(Inverse Gate Electrode Flash)Technology for System-on-a Chip(Special Issue on Nonvolatile Memories)

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