Eliminating Isochronic-Fork Constraints in Quasi-Delay-Insensitive Circuits

スポンサーリンク

概要

• 論文の詳細を見る

• The Quasi-Delay-Insensitive (QDI) model assumes that all the forks are isochronic. The isochronic-fork assumption requires uniform wire delays and uniform switching thresholds of the gates associated with the forking branches. This paper presents a method for determining such forks that do not have to satisfy the isochronic fork requirements, and presents experimental results that show many isochronic forks assumed for existing QDI circuits do not actually have to be "isochronic" or can be even ignored.

• 社団法人電子情報通信学会の論文
• 2003-04-01

著者

• Sretasereekul Nattha

  Faculty Of Engineering The University Of Tokyo

• Nanya Takashi

  Faculty Of Engineering The University Of Tokyo

関連論文

• Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design(IP Design)(VLSI Design and CAD Algorithms)
• Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design
• Eliminating Isochronic-Fork Constraints in Quasi-Delay-Insensitive Circuits
• On the performance of parallel algorithms on a gracefully degrading system achieved through the BSPM
• Integrating Smart Cards into Transaction Schemes

スポンサーリンク