The Phase Locked Loop for Clock Recovery Used in a Single-Chip 4-Channel 155Mb/s CMOS ATM Physical Layer Controller LSI(Special Issue on Multimedia, Network, and DRAM LSIs)

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概要

• 論文の詳細を見る

• The Phase Locked Loop (PLL) for clock recovery used in a single chip 155.52Mb/s×4-Ch CMOS LSI (QPLC) for SONET/SDH termination is described in this letter. This LSI is the first quad-channel ATM physical layer controller chip in which each channel has a clock recovery PLL achieving 55ps rms jitter, using current regulated constant amplitude differential VCO and the triple well structure.

• 社団法人電子情報通信学会の論文
• 1998-05-25

著者

• Nakao Takehiko

  Toshiba Corporation

• KUWAHARA Masanori

  Toshiba Corporation

• OHARA Yasuo

  Toshiba Corporation

• ARIYOSHI Reiji

  Toshiba Microelectronics Corporation

• KITAZUME Toshihiko

  Toshiba Microelectronics Corporation

• SUGAWA Naoki

  Toshiba Microelectronics Corporation

• OGAWARA Takeshi

  Toshiba Information Systems Corporation

• ODA Satoshi

  Toshiba Information Systems Corporation

• NOMURA Shoji

  Toshiba Corporation

• MIYAZAWA Yuichi

  Toshiba Corporation

• KANUMA Akira

  Toshiba Corporation

• Ohara Y

  Keio Univ. Fujisawa‐shi Jpn

関連論文

• Issues of Mixed-Signal Circuit Design in 90nm CMOS LSI Technology
• The Phase Locked Loop for Clock Recovery Used in a Single-Chip 4-Channel 155Mb/s CMOS ATM Physical Layer Controller LSI(Special Issue on Multimedia, Network, and DRAM LSIs)

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