A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture
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概要
- 論文の詳細を見る
This paper describes two new power-saving schemes for high-performance VLSI's with a large-scale memory and many interface signals. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving input buffer (SPSIB) that reduces dc current in interface circuits receiving TTL-high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM.
- 社団法人電子情報通信学会の論文
- 1993-05-25
著者
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Fujimoto Yukihiro
Semiconductor Device Engineering Laboratory Microelectronics Center Toshiba Corporation
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Kobayashi Tsuguo
Semiconductor Device Engineering Laboratory, Microelectronics Center, Toshiba Corporation
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Shirotori Tsukasa
Toshiba Microelectronics Corporation
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Nogami Kazutaka
Semiconductor Device Engineering Laboratory, Microelectronics Center, Toshiba Corporation
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Nogami Kazutaka
Semiconductor Device Engineering Laboratory Microelectronics Center Toshiba Corporation
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Kobayashi Tsuguo
Semiconductor Device Engineering Laboratory Microelectronics Center Toshiba Corporation
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Fujimoto Yukihiro
Ntt Telecommunication Networks Laboratories
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Kobayashi T
Strategic Planning Department National Institute Of Information And Communications Technology
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Kobayashi T
Waseda Univ. Tokyo
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- A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture
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