Minority Carrier Collection in 256 M-bit DRAM Cell on Incidence of Alpha-Particle Analyzed by Three-Dimensional Device Simulation (Special Issue on LSI Memories)

スポンサーリンク

概要

• 論文の詳細を見る

• We studied minority carrier collection in high-density stacked-capacitor DRAM cells using a three-dimensional device simulator. We estimated the collected charge for incident angle, location, and junction size and showed that, compared to the conventional structure by a twin-well process, an n-well-guarded cell array fabricated using a triple-well process effectively reduced the charge injected into cells. The reduction was because the n-well absorbed most of the electrons. A so-called "size-effect" did exist and smaller junctions performed better. We concluded that storage capacitance in a 256 M-bit DRAM cell could be reduced, compared to that in previous devices, which would, in turn, help reduce costs in fabricating high-density DRAM.

• 社団法人電子情報通信学会の論文
• 1993-11-25

著者

• Oshida Sumiko

  Fujitsu Limited

• Taguchi Masao

  FUJITSU LIMITED

関連論文

• High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application (Special Issue on Multimedia, Analog and Processing LSIs)
• Minority Carrier Collection in 256 M-bit DRAM Cell on Incidence of Alpha-Particle Analyzed by Three-Dimensional Device Simulation (Special Issue on LSI Memories)
• Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface (Special Issue on ULSI Memory Technology)

スポンサーリンク