Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface (Special Issue on ULSI Memory Technology)

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概要

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• We report two new timing control methods for high-speed synchronous interfaces in view of their application to high-speed synchronous DRAMs. These two new circuits are the measure-controlled DLL and the register-controlled DLL. We quantitatively analyzed the minimum operational cycle time for a synchronous interface, and related the minimum bus cycle time to two factors; the bus-to-clock timing skew, and the unit delay time of the DLL. Based on this analysis, we concluded that the I/O performance can be beyond 400 MHz by suppressing both factors to less than 200 ps.

• 社団法人電子情報通信学会の論文
• 1996-06-25

著者

• Taguchi Masao

  FUJITSU LIMITED

• Nishimura Koichi

  Fujitsu Limited

• OKAJIMA Yoshinori

  FUJITSU LIMITED

• YANAGAWA Miki

  FUJITSU LIMITED

• HAMADA Osamu

  FUJITSU LIMITED

関連論文

• High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application (Special Issue on Multimedia, Analog and Processing LSIs)
• Minority Carrier Collection in 256 M-bit DRAM Cell on Incidence of Alpha-Particle Analyzed by Three-Dimensional Device Simulation (Special Issue on LSI Memories)
• Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface (Special Issue on ULSI Memory Technology)

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