High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application (Special Issue on Multimedia, Analog and Processing LSIs)

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概要

• 論文の詳細を見る

• High performance I/O circuits for fast memory devices such as Synchronous DRAMs were studied. For a TTL interface, the effect of capacitive loading must increase as I/O speed is increased, and signal termination is required for frequencies over 100 MHz. For this reason, industry-proposed alternative interface approaches such as GTL and CTT were investigated using experimental test devices. The results showed that open-drain type drivers have a problem ; as the frequency increases, the high-level output voltage becomes degraded. In contrast, a push-pull driver T-LVTTL (Terminated Low Voltage TTL), developed as an implementation of the CTT interface specification, was found to be suitable for high-speed data transfer. A high-speed bus driver circuit connecting an impedance element in series to the stub is proposed as an application of T-LVTTL. Simulated results showed that this scheme greatly improves the signal integrity of memory bus systems ; the operating frequency could very well be the highest among several schemes discussed as candidates for the post-LVTTL standard interface.

• 社団法人電子情報通信学会の論文
• 1994-12-25

著者

• Taguchi M

  Mitsubishi Electric Corporation

• Taguchi Masao

  FUJITSU LIMITED

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• High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application (Special Issue on Multimedia, Analog and Processing LSIs)
• Minority Carrier Collection in 256 M-bit DRAM Cell on Incidence of Alpha-Particle Analyzed by Three-Dimensional Device Simulation (Special Issue on LSI Memories)
• Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface (Special Issue on ULSI Memory Technology)

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