Network Resynthesis Algorithms for Delay Minimization (Special Issue on Synthesis and Verification of Hardware Design)

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概要

• 論文の詳細を見る

• Logic synthesizers usually have good area minimization capabilities, producing circuits of minimal area. But good delay minimization techniques are still missing in current logic synthesis technology. In [7], the RENO algorithm (which stands for REsynthesis for Network Optimization) was proposed for minimizing the area of multi-level combinational networks, and its effectiveness in designing minimal-area networks has been demonstrated. In this paper, we present improvements and extensions of the RENO algorithm for network delay minimization by using Boolean resynthesis techniques. We will discuss new algorithms for gate resynthesis which have not only reduced the processing time significantly, but also have improved the quality of minimization. Due to the generality of the gate resynthesis algorithms, we can minimize both delay and area of a network concurrently in a unified way, and network delay is reduced significantly with no or very small area penalty. Extensive experimental results and comparison with the speed-up algorithm [16] in SIS-1.0 are presented.

• 社団法人電子情報通信学会の論文
• 1993-09-25

著者

• Fujita Masahiro

  FUJITSU LABORATORIES LTD.

• Chen Kuang-chien

  Fujitsu America Inc.

関連論文

• Enhanced Unique Sensitization for Efficient Test Generation (Special Issue on Synthesis and Verification of Hardware Design)
• Network Resynthesis Algorithms for Delay Minimization (Special Issue on Synthesis and Verification of Hardware Design)
• Timing Optimization of Multi-Level Networks Using Boolean Relations (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)

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