Timing Optimization of Multi-Level Networks Using Boolean Relations (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)

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概要

• 論文の詳細を見る

• In this paper we propose a new timing optimization technique for multi-level networks by restructuring multiple nodes simultaneously. Multi-output subcircuits on critical paths are extracted and resynthesized so that the delays of the paths are reduced. The complete design space of the subcircuits is captured by Boolean relations, which allow us to perform more powerful resynthesis than previous approaches using don't cares. Experimental results are reported to show the effectiveness of the proposed technique.

• 社団法人電子情報通信学会の論文
• 1993-03-25

著者

• Fujita Masahiro

  FUJITSU LABORATORIES LTD.

• Kukimoto Yuji

  the Faculty of Engineering, The University of Tokyo

• Kukimoto Yuji

  The Faculty Of Engineering The University Of Tokyo

関連論文

• Enhanced Unique Sensitization for Efficient Test Generation (Special Issue on Synthesis and Verification of Hardware Design)
• Network Resynthesis Algorithms for Delay Minimization (Special Issue on Synthesis and Verification of Hardware Design)
• Timing Optimization of Multi-Level Networks Using Boolean Relations (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)

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