SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits (Special Issue on VLSI Testing and Testable Design)

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概要

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• We propose a method of diagnosing any logical fault in combinational circuits through a repetition of the single fault-net location procedure with the aid of probing, called SIFLAP-G. The basic idea of the method has been obtained through an observation that a single error generated on a fault-net often propagates to primary outputs under an individual test even though multiple fault-nets exist in the circuit under test. Therefore, candidates for each fault-net are first deduced by the erroneous path tracing under the single fault-net assumption and then the fault-net is found out of those candidates by probing. Probing internal nets is done only for some of the candidates, so that it is possible to greatly decrease the number of nets to be probed. Experimental results show that the number seems nearly proportional to the number of fault-nets (about 35 internal nets per fault-net), but almost independent of the type of faults and the circuit size.

• 社団法人電子情報通信学会の論文
• 1993-07-25

著者

• Yamazaki Koji

  School Of Information And Communication Meiji University

• Yamada Teruhiko

  School Of Science And Technology Meiji University

関連論文

• A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information
• Post-BIST Fault Diagnosis for Multiple Faults
• Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
• A Single Bridging Fault Location Technique for CMOS Combinational Circuits
• SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits (Special Issue on VLSI Testing and Testable Design)

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