A Single Bridging Fault Location Technique for CMOS Combinational Circuits

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概要

• 論文の詳細を見る

• A single bridging fault location technique for CMOS combinational circuits is proposed. In this technique, the cause of an error observed at the primary outputs is deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is [the number of gates]×[the number of tests]×2 bits, which is much smaller than that of the fault dictionary. The experimental results show that the number of possible bridging faults is reduced to less than 5 in several seconds, when using the tests to detect single stuck-at faults and considering only the bridging faults between physically adjacent nets.

• 社団法人電子情報通信学会の論文
• 1995-07-25

著者

• Yamazaki Koji

  School Of Information And Communication Meiji University

• Yamada T

  Meiji Univ. Kawasaki‐shi Jpn

• Yamada Teruhiko

  School Of Science And Technology Meiji University

• Yamazaki Koji

  School Of Science And Technology Meiji University

関連論文

• A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information
• Post-BIST Fault Diagnosis for Multiple Faults
• Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
• A Single Bridging Fault Location Technique for CMOS Combinational Circuits
• SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits (Special Issue on VLSI Testing and Testable Design)

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