On-Line Error Monitoring for Shared Buffer ATM Switches

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概要

• 論文の詳細を見る

• Shared buffer ATM switches have been attractive since they can achieve a superior performance in terms of cell loss ratio and throughput with a relatively small buffer size. Shared multi-buffer structures have also been considered by several researchers to enhance the access speed of the cell memory for a large switch. High quality services, however, cannot be provided without reliable operation at each module comprising the ATM switches. In this paper, we present a novel on-line error monitoring technique for shared-buffer ATM switches. The technique detects almost all of the functional errors that could occur in the ATM switches. Moreover, it can detect errors with small hardware overhead and negligible time overhead. An early detection of functional errors in ATM switches could not only reduce the wasted bandwidth due to the transmission of erroneous cells, but greatly enhance the recovery time.

• 社団法人電子情報通信学会の論文
• 1999-08-25

著者

• Choi Yun-ho

  Product Development Center Memory Division Samsung Electronics

• Choi Y‐h

  Kangwon National Univ. Kangwon‐do Kor

• CHOI Yoon-Hwa

  Department of Computer Engineering, Hongik University

• LEE Pong-Gyou

  Department of Computer Science, Hongik University

• Lee Pong-gyou

  Department Of Computer Science Hongik University:(present Address) Locus Corporation

• Choi Yoon-hwa

  Department Of Computer Engineering Hongik University

関連論文

• 16-Mb Synchronous DRAM with 125-Mbyte/s Data Rate (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
• Variable V_<CC> Design Techniques for Battery-Operated DRAM's (Special Section on the 1992 VLSI Circuits Symposium)
• On-Line Error Monitoring for Shared Buffer ATM Switches
• Implementation of a High-Performance Genetic Algorithm Processor for Hardware Optimization
• An Efficient Cell Placement Strategy for Shared Multibuffer ATM Switches

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