VLSI Systolic Array for SRIF Digital Signal Processing Algorithm (Special Section of Papers Selected from the 8th Digital Signal Processing Symymposium)

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Kalman filter is an essential tool in signal processing, modern control and communications. The filter estimates the states of a given system from noisy measurements, using a mean-square error criterion. Although Kalman filter has been shown to be very versatile, it has always been computationally intensive since a great number of matrix computations must be performed at each iteration. Thus the exploitation of this technique in broadband real time applications is restricted. The solution to these limitations appears to be in VLSI (very large scale integration) architectures for the parallel processing of data, in the form of systolic architectures. Systolic arrays are networks of simple processing cells connected only to their nearest neighbors. Each cell consists of some simple logic and has a small amount of local memory. Overall data flows through the array are synchronously controlled by a single main clock pulse. In parallel with the development of Kalman filter, the square root covariance and the square root information methods have been studied in the past. These square root methods are reported to be more accurate, stable and efficient than the original algorithm presented by Kalman. However it is known that standard SRIF is less efficient than the other algorithms, simply because standard SRIF has additional matrix inversion computation and matrix multiplication which are difficult to implement in terms of speed and accuracy. To solve this problem, we use the modified Faddeeva algorithm in computing matrix inversion and matrix multiplication. The proposed algorithm avoids the direct matrix inversion computation and matrix multiplication, and performs these matrix manipulations by Gauss elimination. To evaluate the proposed method, we constructed an efficient systolic architecture for standard SRIF using the COMPASS design tools. Actual VLSI design and its simulation are done on the circuits of four type processors that perform Gauss elimination and the modified Givens rotation.
社団法人電子情報通信学会の論文
1994-09-25

VLSI Systolic Array for SRIF Digital Signal Processing Algorithm (Special Section of Papers Selected from the 8th Digital Signal Processing Symymposium)

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