Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories(Integrated Electronics)

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概要

• 論文の詳細を見る

• This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows the smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high bandwidth of 400 MHz operation with CL=2.5.

• 社団法人電子情報通信学会の論文
• 2005-02-01

著者

• YOSHIHARA Tsutomu

  Waseda University

• Miki Takeo

  Memory Development Dept. Renesas Technology Corporation

• Kono Takashi

  Memory Development Dept. Renesas Technology Corporation

• Hamamoto Takeshi

  Memory Development Dept. Renesas Technology Corporation

• Konishi Yasuhiro

  Memory Development Dept. Renesas Technology Corporation

• Furutani Kiyohiro

  Memory Development Dept. Renesas Technology Corporation

• NAKANO Masaya

  Memory Development Dept., Renesas Technology Corporation

• KIKUDA Shigeru

  Memory Development Dept., Renesas Technology Corporation

• Nakano Masaya

  Memory Development Dept. Renesas Technology Corporation

• Kikuda Shigeru

  Memory Development Dept. Renesas Technology Corporation

関連論文

• A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros(Integrated Electronics)
• Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh(Memory, Low-Power LSI and Low-Power IP)
• Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories(Integrated Electronics)

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