Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images

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概要

• 論文の詳細を見る

• This paper describes an improved multiresolution telescopic search algorithm (MRTLlSA) for block-matching motion estimation. The algorithm uses images with full and reduced bit resolution, and uses motion-track and adaptive-search-window strategies. Simulation results show that the proposed algorithm has low computational complexity and achieves good image quality. We have developed a systolic-architecture-based search engine that has split data paths. In the case of low bit-resolution, the throughput is increased by enhancing the operating parallelism. The new motion estimator works at a low clock frequency and a low supply voltage, and therefore has low power consumption.

• 社団法人電子情報通信学会の論文
• 2001-03-01

著者

• Kondo T

  Hiroshima Univ. Higashi-hiroshima‐shi Jpn

• ZHANG Wujian

  Institute of Microelectronics, Tsinghua University

• ZHOU Runde

  Institute of Microelectronics, Tsinghua University

• ISHITANI Tsunehachi

  NTT Electronics Corporation

• KASAI Ryoto

  NTT Electronics Corporation

• KONDO Toshio

  the Department of Information Engineering, Mie University

• KASAI Ryota

  NTT Electronics Corporation

• Kasai R

  Ntt Electronics Corporation

• Zhou Runde

  Institute Of Microelectronics Tsinghua University

• Zhang Wujian

  Institute Of Microelectronics Tsinghua University

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