A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs (Special Issue on Low-Power and High-Speed LSI Technologies)

スポンサーリンク

概要

• 論文の詳細を見る

• A computer-aided low-power design methodology for very high-speed Si bipolar standard cell LSI is described. In order to obtain Gbit/s-speed operation, it features a pair of differential clock channels inside cells and a highly accurate static timing analysis for back annotation. A newly developed CAD-based power optimization scheme minimizes cell currents while maintaining circuit speed. A 5.6 k gate SDH signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design technology.

• 社団法人電子情報通信学会の論文
• 1997-12-25

著者

• Koike Keiichi

  Ntt System Electronics Laboratories

• Takei Yuichiro

  Ntt System Electronics Laboratories

• Ichino Haruhiko

  Ntt Optical Network Systems Laboratories

• Kawai K

  Ntt Optical Network Systems Laboratories

• Onozawa Akira

  Ntt Multimedia Networks Laboratories

• KAWAI Kenji

  NTT Optical Network Systems Laboratories

• KOBAYASHI Yoshiji

  NTT Electronics Technology Corporation

• ONOZAWA AKIRA

  NTT Microsystem Integration Laboratories

関連論文

• Image-Based Photorealistic 3D Reconstruction Using Hexagonal Representation(Computer Graphics)
• Image-Based Photorealistic 3D Reconstruction Using Hexagonal Representation
• A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs (Special Issue on Low-Power and High-Speed LSI Technologies)
• Low-Power Circuit Design Techniques for Si Bipolar Gbit/s LSIs : An Overview (Special Issue on Low-Power and High-Speed LSI Technologies)
• A Balanced-Mesh Clock Routing Technique for Performance Improvement

スポンサーリンク