Low-Power Circuit Design Techniques for Si Bipolar Gbit/s LSIs : An Overview (Special Issue on Low-Power and High-Speed LSI Technologies)

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概要

• 論文の詳細を見る

• This paper surveys low-power design techniques for Si bipolar Gbit/s LSIs. First, a total strategy for power reduction in bipolar LSIs is described. The power dissipation of Si bipolar LSIs can be minimized by reducing the supply voltage, switching and driving currents, the power of input and output circuits, and the equivalent "on" ratio. Widely spread activities from device to architecture levels are indispensable and each of the low-power techniques reduces power by a factor of about 0.5 to 0.7. The integration of these techniques is very important, and as a certain example of their effectiveness, an SOH signal processing LSI is demonstrated with a reduction factor of 1/10. Comparisons with other device technologies for low power characteristics reveal the low-power potential of bipolar LSIs in the Gbit/s region.

• 社団法人電子情報通信学会の論文
• 1997-12-25

著者

• Ichino Haruhiko

  Ntt Electronics Corporation

• Ichino H

  Ntt Electronics Corporation

• Ichino Haruhiko

  Ntt Optical Network Systems Laboratories

関連論文

• Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs : Duplicated Loop Control CDR
• Low-Power 2.5-Gb/s Si-Bipolar IC Chipset for Optical Receivers and Transmitters Using Low-Voltage and Adjustment-Free Circuit Techniques (Special Issue on Ultra-High-Speed IC and LSI Technology)
• A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs (Special Issue on Low-Power and High-Speed LSI Technologies)
• Low-Power Circuit Design Techniques for Si Bipolar Gbit/s LSIs : An Overview (Special Issue on Low-Power and High-Speed LSI Technologies)

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