A Balanced-Mesh Clock Routing Technique for Performance Improvement

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概要

• 論文の詳細を見る

• This paper presents a clock routing technique called Balanced-Mesh Method (BMM) which incorporates the advantages of two famous conventional-clock-routing techniques. One is the balanced-tree method (BTM) where the clock net is routed as a tree so that the delay times of clock signal are balanced, and the other is the fixed-mesh method (FMM) where the clock net is routed as a fixed mesh driven by a large buffer. In BMM, the clock net is routed as a set of relatively small meshes of interconnects driven by relatively small buffers. Each mesh covers an area called a Mesh-Routing Region (MR) in which its delay and skew can be suppressed within a certain range. These small meshes are connected by a balanced tree with the chip clock source as its root. To implement BMM, we developed an MR-partitioning program that partitions the circuit into MR's according to a set of pre-determined constraints on the number of flip-flops and the area in each MR, and a clock-global-routing program that provides each mesh routing and the tree routing connecting meshes. We applied BMM to the design of an MPEG2-encoder LSI and achieved a skew of 210 ps. In addition, the experimental results show BMM yields the lowest power dissipation compared to conventional methods.

• 社団法人電子情報通信学会の論文
• 1997-08-25

著者

• Onozawa Akira

  Ntt Multimedia Networks Laboratories

• Sato Hidenori

  Ntt System Electronics Laboratories

• Matsuda Hiroaki

  Ntt Human Interface Laboratories

関連論文

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• A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs (Special Issue on Low-Power and High-Speed LSI Technologies)
• A Balanced-Mesh Clock Routing Technique for Performance Improvement

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