A 0.9-V, 2.5 MHz CMOS 32-bit Microprocessor
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概要
- 論文の詳細を見る
A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8μm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 mm×7.1 mm die.
- 社団法人電子情報通信学会の論文
- 1995-04-25
著者
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Yano Y
Ulsi Systems Development Laboratories Nec Corporation
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Yano Yoichi
Ulsi Systems Development Laboratories Nec Corporation
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Sakai Tetsushi
Interdisciplinary Graduate School Of Science And Engineering Tokyo Institute Of Technology
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Sakai T
Tokyo Inst. Of Technol. Yokohama-shi Jpn
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Suzuki Hiroaki
ULSI Systems Development Laboratories, NEC Corporation
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Sakai Toshichika
ULSI Systems Development Laboratories, NEC Corporation
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Harigai Hisao
ULSI Systems Development Laboratories, NEC Corporation
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Harigai Hisao
Ulsi Systems Development Laboratories Nec Corporation
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Suzuki Hiroaki
Ulsi Systems Development Laboratories Nec Corporation
関連論文
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- A 0.9-V, 2.5 MHz CMOS 32-bit Microprocessor
- ULSI Memory for Multimedia Applications