Temporal Verification of Real-Time Systems
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概要
- 論文の詳細を見る
This paper presents a general method for computing quantitative information about finite-state real-time systems. We have developed algorithms that compute exact bounds on the delay between two specified events and on the number of occurrences of an event in a given interval. This technique allows us to determine performance measures such as schedulability, response time, and system load. Our algorithms produce more detailed information than traditional methods. This information leads to a better understanding of system behavior, in addition to determining its correctness. The algorithms presented in this paper are efficiently implemented using binary decision diagrams and have been incorporated into the SMV symbolic model checker. Using this method, we have verified a model of an aircraft control system with 10^lt15gt states. The results obtained demonstrate that our method can be successfully applied in the verification of real-time system designs.
- 社団法人電子情報通信学会の論文
- 1995-07-25
著者
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Clarke Edmund
School Of Computer Science Carnegie Mellon University
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Hiraishi Hiromi
Faculty Of Engineering Kyoto Sangyo University
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Campos Sergio
School of Computer Science, Carnegie Mellon University
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Marrero Wilfredo
School of Computer Science, Carnegie Mellon University
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Minea Marius
School of Computer Science, Carnegie Mellon University
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Minea Marius
School Of Computer Science Carnegie Mellon University
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Campos Sergio
School Of Computer Science Carnegie Mellon University
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Marrero Wilfredo
School Of Computer Science Carnegie Mellon University
関連論文
- Formal Verification of Totally Self-Checking Properties of Combinational Circuits
- An Application of Regular Temporal Logic to Verification of Fail-Safeness of a Comparator for Redundant System (Special Issue on VLSI Testing and Testable Design)
- Temporal Verification of Real-Time Systems
- Towards Verification of Bit-Slice Circuits : Time-Space Modal Model Checking Approach
- Symbolic Model Checking of Deadlock Free Property of Task Control Architecture(Special Issue on Test and Verification of VLSI)