Formal Verification of Totally Self-Checking Properties of Combinational Circuits

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概要

• 論文の詳細を見る

• In this paper we propose a method of formal verification of totally self-checking (TSC) properties of combinational circuits using logic function manipulation. We show that the problem of verification of TSC properties can be transformed to a satisfiability problem of decision functions formed from characteristic functions of a circuit's output code words. Then the problem can be solved using binary decision diagrams (BDD). Experimental results show the effectiveness of the proposed method.

• 社団法人電子情報通信学会の論文
• 1997-01-25

著者

• Kawakubo K

  Faculty Of Engineering Fukuyama University

• Tanaka K

  Faculty Of Engineering Fukuyama University:com System Co. Ltd.

• KAWAKUBO Kazuo

  Faculty of Engineering, Fukuyama University

• TANAKA Koji

  Faculty of Engineering, Fukuyama University

• HIRAISHI Hiromi

  Faculty of Engineering, Kyoto Sangyo University

• Hiraishi Hiromi

  Faculty Of Engineering Kyoto Sangyo University

• Kawakubo Kazuo

  Faculty Of Engineering Fukuyama University

関連論文

• Formal Verification of Totally Self-Checking Properties of Combinational Circuits
• An Application of Regular Temporal Logic to Verification of Fail-Safeness of a Comparator for Redundant System (Special Issue on VLSI Testing and Testable Design)
• Temporal Verification of Real-Time Systems
• Towards Verification of Bit-Slice Circuits : Time-Space Modal Model Checking Approach
• Symbolic Model Checking of Deadlock Free Property of Task Control Architecture(Special Issue on Test and Verification of VLSI)

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