Towards Verification of Bit-Slice Circuits : Time-Space Modal Model Checking Approach

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概要

• 論文の詳細を見る

• The goal of this paper is to propose a new symbolic model checking approach named time-space modal model checking, which could be applicable to verification of bit-slice microprocessor of infinite bit width and one dimensional systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.

• 社団法人電子情報通信学会の論文
• 1995-07-25

著者

• HIRAISHI Hiromi

  Faculty of Engineering, Kyoto Sangyo University

• Hiraishi Hiromi

  Faculty Of Engineering Kyoto Sangyo University

関連論文

• Formal Verification of Totally Self-Checking Properties of Combinational Circuits
• An Application of Regular Temporal Logic to Verification of Fail-Safeness of a Comparator for Redundant System (Special Issue on VLSI Testing and Testable Design)
• Temporal Verification of Real-Time Systems
• Towards Verification of Bit-Slice Circuits : Time-Space Modal Model Checking Approach
• Symbolic Model Checking of Deadlock Free Property of Task Control Architecture(Special Issue on Test and Verification of VLSI)

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