A New Rip-Up and Reroute Algorithm for Very Large Scale Gate Arrays (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
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概要
- 論文の詳細を見る
A fast rip-up and reroute algorithm for very large scale gate arrays is proposed. The automatic routing program for gate arrays usually consists of an initial routing process and rip-up and rerouting process. The rip-up and rerouting process eliminates the unconnects introduced by the initial routing process. There are two main reasons for leaving some unconnects: routing order dependency and local wire congestion. The existing rip-up and reroute algorithms can efficiently resolve unconnects caused by the routing order dependency. However, they cannot do unconnects caused by the local wire congestion. On the other hand, the proposed algorithm combines a 'global' and 'local' rip-up and reroute process and efficiently resolve unconnects caused by both of them. The 'global' process reduces the local wire congestion by ripping up and rerouting global paths. The 'local' process eliminates the unconnects, mainly caused by routing order dependency, by ripping up and rerouting local paths. The effectiveness of our method is demonstrated by our experimental results on industrial sea-of-gates (SOG) circuits and a well-known benchmark circuit.
- 社団法人電子情報通信学会の論文
- 1997-03-25
著者
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Terai Masayuki
Manufacturing Technology Division Mitsubishi Electric Corporation
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Terai Masayuki
Manufacturing Technology Division Semiconductor Group Mitsubishi Electric Corporation
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Shirota Hiroshi
Manufacturing Technology Division Semiconductor Group Mitsubishi Electric Corporation
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SHIBATANI Satoshi
Manufacturing Technology Division, Semiconductor Group, MITSUBISHI ELECTRIC CORPORATION
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Shibatani S
Manufacturing Technology Division Semiconductor Group Mitsubishi Electric Corporation
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- Synthesis of Testable Sequential Circuits with Reduced Checking Sequences (Special Issue on VLSI Testing and Testable Design)
- A New Rip-Up and Reroute Algorithm for Very Large Scale Gate Arrays (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)