A CAD-Based Approach to Fault Diagnosis of CMOS LSI with Single Fault Using Abnormal Iddq (Special Section on VLSI Design and CAD Algorithms)

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概要

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• A CAD-based faulty portion diagnosis technique for CMOS-LSI with single fault using abnormal Iddq has been developed to indicate the presence of physical damage in a circuit. This method of progressively reducing the faulty portion, works by extracting the inner logic state of each block from logic simulation, and by deriving test vector numbers with abnormal Iddq. To easily perform fault diagnosis, the hierarchical circuit structure is divided into primitive blocks including simple logic gates. The diagnosis technique employs the comparative operation of each primitive block to determine whether one and the same inner logic state with abnormal Iddq exists in the inner logic state with normal Iddq or not. The former block is regarded as normal block and the latter block is regarded as faulty block. Faulty portion of the faulty block can be localized easily by using input logic state simulation. Experimental results on real faulty LSI with 100 k gates demonstrated rapid diagnosis times of within ten hours and reliable extraction of the faulty portion.

• 社団法人電子情報通信学会の論文
• 1997-10-25

著者

• Sanada M

  Nec Electronics Corp. Kawasaki‐shi Jpn

• Sanada Masaru

  Analysis Technology Development Division Nec Electronics Corporation

関連論文

• A CAD-Based Approach to Fault Diagnosis of CMOS LSI with Single Fault Using Abnormal Iddq (Special Section on VLSI Design and CAD Algorithms)
• Layout-Based Detection Technique of Line Pairs with Bridging Fault Using I_(Fault Detection)(Test and Verification of VLSI)

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