A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• A timing-driven global routing algorithm is proposed that directly models the path-based timing constraints. By keeping track of the critical path delay and channel densities, and using novel heuristic criteria, it can select routing paths that minimize area as well as satisfy the timing constraints. Using bipolar-specific features, this router can be used to design LSI chips that handle signals with speeds greater that a gigabit per second. Experimental results shows an average delay improvement of 17.6%.

• 社団法人電子情報通信学会の論文
• 1994-12-25

著者

• TAKEI Yuichiro

  The authors are with the NTT Integrated Information and Energy Systems Laboratories

• Takei Y

  Department Of Electrical Engineering Nagaoka University Of Technology

• Kitazawa H

  Ntt Integrated Information And Energy Systems Lab. Atsugi‐shi Jpn

• Harada Ikuo

  NTT System Services Dept.

• Takei Yuichiro

  NTT LSI Laboratories

• Kitazawa Hitoshi

  NTT R&D Management Dept.

• Kitazawa Hitoshi

  Ntt R&d Management Dept.

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• A 40-Gb/s 8×8 ATM Switch LSI Using 0.25-μm CMOS/SIMOX(Special Issue on Multimedia, Network, and DRAM LSIs)
• A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs (Special Section on VLSI Design and CAD Algorithms)

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