Reuse Design of Run Length Coder using VHDL
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概要
- 論文の詳細を見る
In this paper, we describe the interface specification and core block design methods for Run Length Coder of video compression application. It offers high performance and many features to meet multimedia, and digital video applications. We design VLSI architecture of run length coder using VHDL. This design can achieve the high performance for video coder, is based on H.263 Recommendation. The format of the outputs is compatible with the stream of the Variable Length Coding. Run Length Coder is implemented by register transfer level(RTL) of VHDL. The designed block is synthesized by Compass synthesis with 0.5um CMOS, 3.3V, technology and reuse as core IP(Intellectual Property) of H.263 and MPEG4 application. The run length coder block contains 4,000 logic gates and total 1,536 bits of Static RAM. The designed block is synthesized by Compass synthesis with 0.5μm CMOS, 3.3V, technology. Fully synchronous design allows for fast operation while maintaining a low gate count. The core will reuse to multimedia system and digital video applications.
- 社団法人電子情報通信学会の論文
- 1999-07-22
著者
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Cho Hanjin
Department Of Integrated Circuits Design Electronics And Telecommunications Research Institute
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Cho Hanjin
Micro Electronics Technology Lab. Electronics And Telecommunications Research Institute
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Cho H
Electronics And Telecommunications Res. Inst. Daejeon Kor
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Park Seongmo
Department of Integrated Circuits Design, Electronics and Telecommunications Research Institute
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Kim Seongmin
Department of Integrated Circuits Design, Electronics and Telecommunications Research Institute
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Park Inhag
Department of Integrated Circuits Design, Electronics and Telecommunications Research Institute
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Cha Jinjong
Department of Integrated Circuits Design, Electronics and Telecommunications Research Institute
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Park I
Etri Taejon Kor
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Cha Jinjong
Department Of Integrated Circuits Design Electronics And Telecommunications Research Institute
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Park S
Electronics And Telecommunications Res. Inst. Daejeon Kor
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Kim Seongmin
Department Of Integrated Circuits Design Electronics And Telecommunications Research Institute
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