IP Interface Design Experiences with an On-Chip Bus

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概要

• 論文の詳細を見る

• Integration of IP cores through an on-chip bus is a process of converting IP communication protocols to a common bus protocol. To integrate IP cores it is necessary to design interface circuits between those cores and the master or slave bus interface. In addition, memory spaces should be allocated for the transactions to the slave cores in the interface design process. This paper presents some empirical considerations on IP interface design for an on-chip PI bus.

• 社団法人電子情報通信学会の論文
• 1999-07-22

著者

• Jhang Kyoung-son

  Hannam University

• Eum N‐w

  Etri Taejon Kor

• Joo Joo-Byung

  Electronics and Telecommunications Research Institute

• Eum Nak-Woong

  Electronics and Telecommunications Research Institute

• Park Inhag

  Electronics and Telecommunications Research Institute

• Park Inhag

  Department of Integrated Circuits Design, Electronics and Telecommunications Research Institute

• Park I

  Etri Taejon Kor

• Jhnag Kyoung-Son

  Hannam University

関連論文

• IP Interface Design Experiences with an On-Chip Bus
• IP Interface Design Experiences with an On-Chip Bus
• IP Interface Design Experiences with an On-Chip Bus
• Reuse Design of Run Length Coder using VHDL
• Reuse Design of Run Length Coder using VHDL
• Reuse Design of Run Length Coder using VHDL

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