High Speed Search and an Area Efficient Huffman Decoder (Special Section of Papers Selected from ITC-CSCC '98)

概要

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In this paper, we present a simple codeword length generation algorithm and its hardware implementation. The proposed technique is based on the dividing the Huffman table as two parts; with leading O'bits and following bits. The method is shown to be efficient in the memory requirement and searching speed since only logic gates are needed in the implementation and searching can be process parallel without looking up the memory table. The total equivalent gates for the implementation are about only 100 gates and critical path delay is 10 ns. The results of experiments show that the proposed algorithm Has a very high speed and a good performance. The designed blocks are synthesized by Compass synthesis with 0.5 μm CMOS, 3.3V, technology.
社団法人電子情報通信学会の論文
1999-06-25