III-V/Siミスマッチ系における転位操作(<小特集>ヘテロエピタキシーと界面構造制御)

概要

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Two mismatches are involved in III-V/Si. One is the large lattice mismatch between a III-V and Si crystal. The other is the large difference in the thermal expansion coefficients between them, in other words, the thermal mismatch. We would like to discuss the dislocation reactions in such mismatched III-V /Si systems from the viewpoint of the lattice mismatch and of the thermal mismatch. With regard to the lattice mismatch, we show the dislocationdensity dependence on III-V film thickness, we show that the dislocation density can be reduced by thermal cyclic annealing and by using strained-layer super-lattices, and we show 2-3 dimensional growth modes in the initial stage of III-V /Si heteroepitaxy. With regard to the thermal mismatch, we show the dislocation generation in the cooling stage from growth temperature to room temperature and the reduction of dislocation generation by slow cooling. The results show that the dislocation density is reduced by controlling the dislocation reactions under stress.
日本結晶成長学会の論文
1998-03-30