B303 DEVELOPMENT OF THE FAIL-SAFE SINGLE CHIP RISC-CPU BOARD
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概要
- 論文の詳細を見る
One configuration of FS-Computer is composed of dual-CPU, dual-peripheral circuits and checking-circuits which supervise dual-CPU and peripheral circuits always running synchronously each other. We introduced the new idea of safety to implement such FS-CPU within a single chip LSI fail-safely, namely using PN-code to detect the failure of intemal circuits and so on. In this article, we address the concept of the safety of dual-CPU in a single chip and its verification.
- 一般社団法人日本機械学会の論文
著者
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NAKAMURA Hideo
College of Science and Technology, Nihon University
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Takahashi Sei
College Of Science & Technology Nihon University
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Takahashi Sei
College Of Science And Technology Nihon University
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Kajiwara Toshihiko
The Nippon Signal Co. Ltd.
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Taira Munehisa
The Nippon Signal Co., Ltd.
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Saegusa Hidetaka
The Nippon Signal Co., Ltd.
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Saegusa Hidetaka
The Nippon Signal Co. Ltd.
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Nakamura Hideo
College Of Science & Technology Nihon University
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Nakamura Hideo
College Of Science And Technology Nihon University
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Taira Munehisa
The Nippon Signal Co. Ltd.
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