A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF)

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概要

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• A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.

• 2012-06-01

著者

• Wang Yuan

  Department Of Animal Resource & Science Dankook University

• LIU Limin

  Department of Microelectronics, Peking University

• LI Xiayu

  Department of Microelectronics, Peking University

• JIA Song

  Department of Microelectronics, Peking University

• WANG Yuan

  Department of Microelectronics, Peking University

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• A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF)

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