DSP-Based Parallel Implementation of Speeded-Up Robust Features

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概要

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• Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.

• 2011-04-01

著者

• WANG Guijin

  Department of Electronic Engineering, Tsinghua University

• Wang Guijin

  Department Of Electronics Engineering Tsinghua University

• Wang Guijin

  Dept. Of Electronic Engineering Tsinghua University

• Lin Xinggang

  Department Of Electronic Engineering Tsinghua University

• MIAO Quan

  Department of Electronic Engineering, Tsinghua University

• Miao Quan

  Department Of Electronic Engineering Tsinghua University

• Liao Chao

  Department Of Electronic Engineering Tsinghua University

• WANG Zhiguo

  Department of Electronic Engineering, Tsinghua University

• SHI Chenbo

  Department of Electronic Engineering, Tsinghua University

• Shi Chenbo

  Department Of Electronic Engineering Tsinghua University

• Wang Zhiguo

  Department Of Electronic Engineering Tsinghua University

• Wang Guijin

  Department Of Electronic Engineering Tsinghua University

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