Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction
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概要
- 論文の詳細を見る
Two-step physical register deallocation (TSD) is an architectural scheme that enhances memory-level parallelism (MLP) by pre-executing instructions. Ideally, TSD allows exploitation of MLP under an unlimited number of physical registers, and consequently only a small register file is needed for MLP. In practice, however, the amount of MLP exploitable is limited, because there are cases where either 1) pre-execution is not performed; or 2) the timing of pre-execution is delayed. Both are due to data dependencies among the pre-executed instructions. This paper proposes the use of value prediction to solve these problems. This paper proposes the use of value prediction to solve these problems. Evaluation results using the SPECfp2000 benchmark confirm that the proposed scheme with value prediction for predicting addresses achieves equivalent IPC, with a smaller register file, to the previous TSD scheme. The reduction rate of the register file size is 21%.
- 2010-12-01
著者
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Ando Hideki
Department Of Electrical Engineering And Computer Science Nagoya University
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Ando Hideki
Department Of Biology Faculty Of Science Okayama University
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Tanaka Yusuke
Department Of Computational Science And Engineering Nagoya University
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Tanaka Yusuke
Department Of Chemistry And Chemical Biology Graduate School Of Engineering Gunma University
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Tanaka Yusuke
Department Of Applied Chemistry Graduate School Of Engineering Kyushu University
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