A New Low-Power 13.56-MHz CMOS Ring Oscillator with Low Sensitivity of f_<OSC> to V_<DD>
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概要
- 論文の詳細を見る
A design of a low-power CMOS ring oscillator for an application to a 13.56MHz clock generator in an implantable RFID tag is proposed. The circuit is based on a novel voltage inverter, which is an improved version of the conventional current-source loaded inverter. The proposed circuit enables low-power operation and low sensitivity of the oscillation frequency, fOSC, to decay of the power supply VDD. By employing a gm-boosting subcircuit, power dissipation is decreased to 49μW at fOSC=13.56MHz. The sensitivity of fOSC to VDD is reduced to -0.02 at fOSC=13.56MHz thanks to the use of composite high-impedance current sources.
- （社）電子情報通信学会の論文
- 2008-02-01
著者
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INOUE Takahiro
Department of Computer Science and Electrical Engineering, Graduate School of Science and Technology
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TSUNEDA Akio
Department of Computer Science and Electrical Engineering, Graduate School of Science and Technology
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Inoue Takahiro
Department Of Cardiovascular Medicine Graduate School Of Medical Sciences Kyushu University
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Tsuneda Akio
Department Of Computer Science And Communication Engineering Kyushu University
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Tsuneda Akio
Dep. Of Computer Sci. And Electrical Engineering Graduate School Of Sci. And Technol. Kumamoto Univ.
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TIMISCHL Felix
Department of Computer Science and Electrical Engineering, Graduate School of Science and Technology
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MASUNAGA Daisuke
Department of Computer Science and Electrical Engineering, Graduate School of Science and Technology
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Masunaga Daisuke
Department Of Computer Science And Electrical Engineering Graduate School Of Science And Technology
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Timischl Felix
Department Of Computer Science And Electrical Engineering Graduate School Of Science And Technology
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Inoue Takahiro
Department Of Anatomic Pathology Graduate School Of Medical Sciences Kyushu University
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Inoue Takahiro
Department Of Computer Science And Electrical Engineering Graduate School Of Science And Technology Kumamoto University
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