High Gain and Wide Range Time Amplifier Using Inverter Delay Chain in SR Latches

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概要

• 論文の詳細を見る

• This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13µm standard CMOS technology and the experimental results agree well with the theory.

• （社）電子情報通信学会の論文
• 2009-12-01

著者

• Lee Sungho

  Seoul National University

• Nam Sangwook

  Seoul National University

• LEE Jaejun

  Seoul National University

• SONG Yonghoon

  Seoul National Univ.

• Nam Sangwook

  Seoul National Univ.

• Lee Jaejun

  Seoul National Univ.

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